Chao Zhang

Chao Zhang is a Component Design Engineer at Intel Corporation since November 2014, with prior experience as an ASIC Customer Engineer at LSI Corporation from July 2011 to March 2014, and a Research Intern at Anzenna, Inc. in early 2011. Chao has a strong background in design implementation, biosensor chip testing, and ASIC/FPGA design, acquired through roles at Polytechnic Institute of New York University where responsibilities included frontend design, schematic/layout verification, and technical reporting. Chao holds a Master’s degree in Computer Engineering from New York University - Polytechnic School of Engineering and a Bachelor’s degree in Microelectronics from East China Normal University.