David Levy has over 19 years of experience at Intel Corporation, currently serving as a Post Si PnP Power Management Validation Engineering Technical Lead since August 2012. In this role, David focuses on the validation and optimization of power management features, collaborating closely with PM and AI Architects to enhance Gen 12th CPU performance. Previously, David held positions such as Staff Product Quality and Reliability Engineer, where innovative testing solutions were developed for infant mortality detection, and Integration Engineer, overseeing technology transfer and certification for 22nm Hi-k Gate and Metal gate technologies. David's educational background includes a Master of Science in Electrical and Electronics Engineering from Tel Aviv University, obtained between 2001 and 2004.
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