Eric Padilla

Eric Padilla is an experienced Senior Equipment and HPM Engineer at Intel Corporation, where since July 2012, strategies have been developed and executed to enhance tool uptime and reliability in Dry Etch toolsets at Intel Fab 42. Eric’s role encompasses managing large projects and mentoring teammates while serving as a technical resource. Prior experience includes serving as a Dry Etch Process Engineer - Tool Owner at Intel Fab 32, where maintenance of VLSI Dry Etch systems was sustained, and as a Rotation Engineer, encompassing process engineering in Thin Film deposition, Dry Etch, and data visualization. Academic qualifications include a Master's degree in Materials Science and Engineering from Arizona State University and a Bachelor's degree in Materials Engineering from UCLA.