Girish Vats is a Tech Lead for Physical Design at Intel Corporation in Bangalore. They have previously held roles such as Soc Design Lead at Intel and Senior Design Engineer for Avago Technologies while working at EInfochips from 2012 to 2014. From 2015 to 2017, Girish served as a Senior Technical Analyst at UST Global, focusing on structural design as a Lead Engineer in Intel Malaysia. They earned a B.Tech in Electronics & Communications from U.P Technical University and an M.Tech in VLSI from ABV-Indian Institute of Information Technology and Management.
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