hareesh babu P.

Hareesh Babu P. is a Senior SOC Verification Engineer with extensive expertise in SOC/IP/subsystem pre-silicon verification, particularly in design for debug and Ethernet MAC validation. They have previously worked at AMD, Intel Corporation, and Mindlance Technologies, focusing on high-speed Ethernet IP validation and post-silicon debug support. Hareesh holds a Bachelor of Engineering in Electrical, Electronics, and Communications Engineering from JNTUK and is currently pursuing further education at Vikashighschool.