Hsing-Min Chen

Hsing-Min Chen is a Silicon Architecture Engineer with a PhD in Electrical and Electronics Engineering from Arizona State University. With extensive research experience, they designed low-cost error correction schemes for DRAM systems at Arizona State University, demonstrating significant improvements in reliability and performance. Currently, at Intel Corporation, Hsing-Min focuses on CPU RAS and server memory reliability. They possess strong programming skills in C/C++, Python, and Verilog, and have actively contributed to studies in memory reliability and performance evaluation.