Indranil Pal

Indranil Pal is an experienced professional at Intel Corporation since September 2004, currently serving as Manager and IP Logic Architect. His expertise includes driving memory interface IP development for high-performance data center microprocessors, with a focus on architecture, design, verification, and post-silicon validation of DDR PHY IP. Previous roles at Intel encompass leading architecture and verification for memory PHY IP and mixed-signal verification for server CPU designs, contributing to significant innovations in verification strategies. Indranil began a career at Cadence Design Systems as a Member of Technical Staff, focusing on the verification of simulation tools. Indranil holds a Bachelor of Engineering degree in Electronics and Tele-communication from Jadavpur University, earned in 2002.