Irene Cheung has extensive experience in the semiconductor industry, currently serving as a Wafer Assembly TD FE Technical Program Manager at Intel Corporation since November 2021, following a tenure as an NVM Senior Process Integration Engineer. Prior experience includes a long-term role at Micron Technology, where Irene held various positions, including DRAM Principal Process Integration Engineer and DRAM Sr Process Integration Engineer, focusing on process development in DRAM technology. Irene's earlier work includes a Senior Scientist position at Quanlight, Inc., conducting wafer characterization and analysis for LED development, and postdoctoral fellowships at the Pacific Northwest National Laboratory and the University of Wisconsin - Milwaukee, specializing in electronic structure characterization and MBE growth of spintronics materials. Irene holds a PhD in Physics from The University of Hong Kong, earned between 1998 and 2002.
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