Jaidev Kaushik is an experienced Physical Design Engineer currently working at Intel Corporation since June 2019. Prior to this role, Jaidev worked at Mindlance Technologies as a Physical Design Engineer from July 2018 to June 2019 and completed a Physical Design Traineeship at Cadence INNOVUS from February 2018 to June 2018. Additional experience includes serving as a Post Silicon Validation Engineer at Tessolve Semiconductor PVT LTD from December 2016 to February 2018 and a Research Intern at GNDEC EDA LAB from July 2015 to June 2016, focusing on various advanced design technologies. Jaidev holds an M.TECH in ECE/VLSI from GNDEC Ludhiana and a B.TECH in ECE from RTU Kota, alongside a 12th-grade qualification in PCM from SSSSS BHADRA.
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