JR

Jayasuriya R

Technical Architect

Jayasuriya R is currently a Technical Architect at Intel Corporation, focusing on design for debug architecture involving Intel and ARM IPs. Previously, Jayasuriya served as a Principal Design Engineer at Microchip Technology Inc. and held positions at Canon and Eaton Corporation, where they specialized in SoC integration and design. With an MTech in Electronics Design Technology from the Indian Institute of Science and a BTech in Electronics from Cochin University of Science and Technology, Jayasuriya has extensive experience in digital design and development across various platforms, including SoC, FPGA, and microcontrollers.

Location

Bengaluru, India

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