Jaymeen Aseem

Jaymeen Aseem is a Memory Design Lead at Intel Corporation in India, with a decade of industry experience in memory circuit design and verification. They previously worked as an SRAM Memory Compiler Design Engineer at TSMC, where they contributed to high-speed, low-power memory designs and were part of an esteemed SRAM compiler team. At Intel, Jaymeen has developed various Read-Only Memory compilers and has been involved in enhancing memory IP performance through logic optimization and developing automation flows. They hold a Master of Technology in Integrated Electronics and Circuits from the Indian Institute of Technology, Delhi, and a Bachelor of Technology in Electrical, Electronics, and Communications Engineering from Nirma University.