Jooho Park

Jooho Park is an accomplished Engineering TD Manager at Intel Corporation, overseeing defect reduction and process improvement in next-generation CMOS process BEOL interconnect technology since August 2005. With a strong background in both 45nm and 22nm CMOS process technologies, Jooho has led significant projects, including industry-first advancements in HiK/Metal gate transistors and Tri-gate 3-D transistors. Prior experience includes roles as a Senior Process Engineer involved in high-volume manufacturing technology transfers, a Consultant and Technical Assistant at Macalester College focusing on semiconductor processing, and Graduate Research Assistant positions at the University of Minnesota and the University of Buffalo specializing in magneto-optic research and semiconductors. Jooho holds a PhD in Condensed Matter and Materials Physics from the University of Minnesota, along with a Master's degree from the State University of New York at Buffalo and a Bachelor of Science from Chung-Ang University, Seoul.