Joseph Mously

Joseph Mously is currently a Pre/Post Silicon Validation FPGA team leader at Intel Corporation and also leads the Logic Design for FPGA based systems at Mobileye. In their previous role as a Software Engineer at Marvell Israel Ltd., they designed C++ based projects for SOC systems and conducted pre/post-silicon validation while integrating RTL code for FPGA. Joseph is studying Computer Software Engineering at Ort Braude College.