Jun Liao

Jun Liao is a Principal Engineer at Intel Corporation, where they focus on memory subsystems, bus design, and interconnect/signal integrity, along with developing analog IO features for high-speed buses and technology enabling LPDDR/DDR. Prior to their current role, Jun served as a Senior Engineer at Altera Corp from 2010 to 2012, working on FPGA system hardware. Jun is currently pursuing a PhD in Electrical Engineering at Rensselaer Polytechnic Institute.