Kaiwalya Patil is a seasoned semiconductor design engineer with over 16 years of experience, currently serving as a Principal Engineer in the Device Development Group at Intel Corporation. They have previously held the role of Senior Design Engineer, where they successfully led multiple SoC design lifecycles and facilitated cross-functional collaborations to deliver high-performance, low-power solutions. In their early career, Kaiwalya contributed to significant integration enhancements that streamlined processes and improved quality metrics across various Intel projects. They hold a Master's degree in Electrical and Electronics Engineering from the University of Rochester.
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