Lavina Sanadhya

Lavina Sanadhya is a Pre-Si Validation and Verification Engineer at Intel, bringing expertise in ASIC verification and a strong foundation in various protocols including I2C and AXI. Previously, Lavina worked as a DV Engineer at eInfochips, where they developed advanced verification environments and testbench components using System Verilog and UVM methodology. Lavina completed a B.Tech in Electronics and Communications Engineering from Geetanjali Institute of Technical Studies in 2019, demonstrating a solid academic background in their field. Additionally, Lavina gained practical experience during an internship at eiTRA, focusing on ASIC verification modules and scripting languages.