Madhav Lekkala

Madhav Lekkala is a Senior SoC Design Verification Engineer at Intel, specializing in SystemVerilog testbench development using OVM/UVM methodologies, and focuses on automation through Python and Tcl. With prior experience as an Assistant Executive Engineer at Indian Telephone Industries Limited and intern roles at various prestigious institutions, Madhav has honed skills in formal verification for complex SoCs and has a proven track record of enhancing verification workflows. Madhav holds a Master of Technology in Electrical Engineering from the Indian Institute of Technology, Delhi, and a Bachelor's degree in Electrical and Electronics Engineering from the Indian Institute of Technology, Palakkad.