Marc D'Angelo has over 25 years of experience in the semiconductor industry, currently serving as a Physical Design Engineer at Intel Corporation since December 2012, focusing on RF and ROM IC layout work. Prior to this role, Marc held positions at Intel Corporation as a Mask Designer from November 1996 to October 2005, leading teams in custom digital layout projects for CPU and chipset groups. From October 2005 to December 2012, Marc worked at AMD as a Mask Designer in the Analog group, specializing in various macro constructions and employing advanced device matching strategies. Marc's educational background includes an Associate of Applied Science in Electromechanical Drafting, a Certificate of Completion in Architectural Drafting, and a Certificate of Completion in Computer-Aided Drafting from Mesa Community College, as well as a Bachelor of Fine Arts in Photography from Arizona State University. Proficient in tools such as Cadence, Mentor Graphics, and Calibre, Marc combines technical expertise with a strong foundation in design principles and team leadership.
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