MP

Maunank Patel

Graphics Hardware Validation Engineer

Maunank Patel is an experienced engineer with a strong background in hardware validation and development. At Intel Corporation from July 2010 to May 2016, Maunank served as a Data Center Hardware Validation and Debug Engineer, working on three complete product life cycles of Xeon Server Family Processors and leading multi-socket board bring-up efforts. After a brief role as a Product Development Engineer at Advanced Micro Devices in 2008, Maunank returned to Intel in December 2016 as a Graphics Hardware Validation Engineer, focusing on functional validation for various Intel graphics products. Maunank holds a Master of Science in Nano Scale Semiconductor Technology from California State University-Sacramento and a Bachelor of Engineering in Electronics & Communication.

Location

Sacramento, United States

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