Navin Srivastava is a seasoned Software Engineer currently at Intel Corporation since October 2022, previously serving as an R&D Engineer at Synopsys from January 2019 to October 2022. At Synopsys, Navin was the architect of StarRC's inductance extraction solutions and a technical lead in transistor-level extraction projects. Prior experience includes significant roles at Mentor Graphics, where Navin contributed to layout pattern matching and parasitic extraction tools, and Atrenta, focusing on high-level code analysis for design rule adherence. As a Graduate Student Researcher at UCSB, Navin developed innovative techniques for high-frequency parasitic extraction and published influential works on carbon nanotube interconnects. Navin holds a PhD in Electrical and Computer Engineering from UC Santa Barbara, obtained in 2009.
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