Peter Sun

Peter Sun has extensive experience in analog design engineering, with a focus on mixed-signal circuits and low jitter PLL design for Intel's Client CPU products. Peter's career began with internships at Vate Technology Co., LTD and TSMC, where contributions included improving testing efficiency and analyzing SRAM performance. Following these internships, Peter served as an Analog Design Engineer at Intel Corporation from June 2018 to June 2020, working on key components for 3DXP Memory. Since June 2020, Peter has continued at Intel Corporation, further developing skills in silicon debugging and characterization. Peter holds a Master of Science in Electrical Engineering and Computer Science from the University of Michigan and two Bachelor's degrees in Electrical and Computer Engineering from National Chiao Tung University and Electrical and Electronics Engineering from Nanyang Technological University.