Pradeep Patlolla

Pradeep Patlolla is a Silicon Architecture Engineer at Intel, bringing over 19 years of experience in ASIC front-end verification activities and technologies. They previously held roles as a Senior Design Engineer at Xilinx, a Senior DV Engineer at Soft Machines Inc., and an ASIC Verification Engineer at Synopsys. Pradeep also contributed to SoC verification and methodology development in earlier positions at Conexant and Raza Microelectronics. Their expertise includes the use of System Verilog and various verification methodologies.