PJ

Prakeerthi J.

Design Verification Manager

Prakeerthi J. is currently a Formal Verification Lead/Mgr for Data Center Xeon SOCs at Intel, where they oversee the end-to-end Formal Validation Staging and have significantly improved the product validation lifecycle efficiency. Previously, Prakeerthi held various positions in ASIC and verification engineering at companies such as Micron Technology, Qualcomm, and Microsoft, building a robust foundation in verification strategies. Prakeerthi earned a Master of Technology (M.Tech.) from B. M. S. College of Engineering through a scholarship from the Indian Institute of Technology, Bombay. Their strategic advancement of Formal initiatives has driven impactful collaboration and innovation across teams.

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San Francisco, United States

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