Rami Busool

Rami Busool is a Senior Tech Lead specializing in CPU microarchitecture and RTL logic design at Intel Corporation, where they lead power reduction initiatives across Intel's inner core clusters. Previously, Rami worked as a Senior FPGA Design Engineer at Active Silicon and held various roles in ASIC/VLSI design and verification at companies including Conexant, Harmonic, and Compass-Eos. Rami’s expertise covers VLSI, ASIC, and FPGA hardware architecture design, and they have also contributed to the development of next-generation Ethernet controllers and high-speed interfaces. Rami is currently pursuing a Master of Business Administration in Entrepreneurship at Tel Aviv University.