Rohit Daroch

Rohit Daroch is a Senior RTL Design Engineer currently at Intel, with over 8 years of experience in RTL design and debugging for various next-generation SOC projects. Previously, Rohit served as an IP Logic Design Engineer at Intel, where they developed and implemented new IPs for advanced server SOCs. They began their career as an Industrial Engineering Intern at Eaton, where they created an Automation Test Framework. Rohit holds a dual degree in Electrical Engineering and Information and Communication Technology from the Indian Institute of Technology, Delhi.