Satish D.

Satish D. is a skilled Technical Lead and Team Architect with expertise in digital design and advanced verification techniques at both the IP and SOC levels. With a Bachelor of Technology in Electrical, Electronics, and Communications Engineering, Satish has held various roles, including Staff Engineer at Intel Corporation, where they work on PCIe subsystems and manage a team of engineers. Their previous experience includes positions at Cypress Semiconductor Corporation, Marvell Semiconductor, and Analog Devices, highlighting a strong background in ASIC verification and problem-solving within the semiconductor industry. Satish's proficiency spans areas like RTL design, test case development, and system-level debugging, with a clear understanding of object-oriented programming and System Verilog.