Shaiful Alam

Shaiful Alam is a Full Chip Timing Lead at Intel Corporation, where they drive full chip STA flow and methodology while ensuring timing closure for advanced technology nodes. With over 20 years of expertise, Shaiful previously served as a Physical Design Manager at Marvell Semiconductor, leading design efforts for cellular and application processor chips. Their earlier experience includes roles at Intel and Actel Semiconductor, where they focused on physical design, FPGA tools, and customer support. Shaiful holds a Master’s degree in Electrical Engineering from Wichita State University and a Bachelor’s degree from Bangladesh University of Engineering and Technology.