Shiva Kumar has a diverse background in layout engineering, with experience spanning over a decade across multiple esteemed companies. Starting as a Trainee Engineer at KarMic Design Private Ltd, Shiva Kumar contributed to standard cell library development and analog layout design. Subsequent roles included Layout Design Engineer at Sankalp Semiconductor, where management of power management blocks for Texas Instruments was a key responsibility, and Layout Engineer at UST Global, collaborating with the Intel flow and the GPIO team in Malaysia. At Cerium Systems Pvt Limited, Shiva Kumar served as a Layout Engineer before advancing to Lead Engineer at Aricent, overseeing complex projects from inception to handoff. Currently, Shiva Kumar holds the position of Analog Layout Methodology Engineer at Intel Corporation, continuing to enhance expertise in the field.
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