Stephen Ramey is an accomplished Engineering Manager at Intel, with a career spanning from October 2003 to the present. Ramey leads the transistor reliability group, focusing on the development of logic CPU process technologies in research and development. Notably, Ramey directed a seven-year project that successfully guided the innovative 22nm tri-gate technology from concept through R&D to commercialization. Prior to Intel, Ramey served as a Research Engineer at Solid State Measurements from June 1997 to July 2000, where the development of hardware, software, and applications for spreading resistance and CV metrology systems took place, contributing to advancements for companies such as Motorola and Siemens. Ramey holds a Ph.D. in Electrical Engineering from Arizona State University, as well as an MS in Electrical Engineering from the University of Nevada-Las Vegas and a B.S. in Physics from Carnegie Mellon University.
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