subarna panda

Subarna Panda is a Senior Physical Design Engineer with 10 years of experience in ASIC Design. They possess in-depth knowledge of various IP levels, including place and route, clock tree synthesis, and verification methodologies such as UVM and OVM. Subarna has been responsible for the design flow from PPA through synthesis to GDSII and post-silicon debug. Currently, they work at Intel Corporation, having previously held roles at Synapse Design Inc. and Infotech Enterprises Ltd. Subarna earned a B.Tech in Electronics and Communication Engineering from NM Institute of Engineering and Technology, BBSR, in 2011.