Subhashini Ramesh

Subhashini Ramesh is a seasoned professional with diverse experience in engineering and mentoring. Key roles include a Java Software Design Engineer at Nokia Networks, where responsibilities encompassed developing software for 4G LTE mobile networks, and a Silicon Validation Engineer at Intel Corporation. Subhashini also served as a Grader and Viterbi Graduate Student Mentor at the University of Southern California, providing valuable support and guidance to new international graduate students. Earlier positions included a Project Trainee at the Centre for Artificial Intelligence and Robotics and a Junior Engineer at Esencia Technologies Inc., complemented by a CAD Engineer role at Microchip Technology Inc. Subhashini holds a Master of Science in VLSI Design and Computer Architecture from the University of Southern California and a Bachelor of Engineering in Electronics and Communications Engineering.