Sudher Kumar Deene

Sudher Kumar Deene is a seasoned ASIC/FPGA Verification Engineer currently working as a Component Design Engineer at Intel Corporation since 2016. With extensive experience in pre-silicon validation across various domains, Sudher has held positions at notable companies including Synopsys and QLogic. They have demonstrated expertise in architecting scalable System Verilog UVM/OVM testbenches and mentoring engineers, reflecting strong technical leadership skills. Sudher holds a Bachelor of Engineering in Electrical, Electronics, and Communications Engineering from PDA College of Engineering and a Diploma in VLSI Design from V3Logic PVT LTD.