Surendra Babu is currently a Technical Lead at Intel Corporation, serving as a CPU Design Engineer with over 12 years of experience in layout verification signoff engineering. They have worked extensively in various stages of VLSI signoff during closure, focusing on block-level and CPU core subsystem verification. Prior to Intel, Surendra held the position of Technical Lead Engineer at Aricent from 2012 to 2018. They earned a Master’s Degree in VLSI and Embedded Design from Visvesvaraya Technological University between 2006 and 2009.
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