Tim Hoang is currently a Hardware Architect at Intel Corporation, where they design and implement multi-Gbps clock data recovery circuits and define top-level architecture to support various protocols. Tim also has extensive experience from their previous role as a Principal Design Engineer at Altera, which they held from 1993 to 2016. They hold a Bachelor of Science degree in Electrical Engineering from the University of California, Berkeley, completed in 1993, and are currently pursuing further education at PetrusKy. Tim is skilled in communicating complex technical issues and collaborating with cross-functional teams to develop engineering solutions.
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