Vijaya Iyer

Vijaya Iyer is a Senior Component Design Engineer at Intel Corporation, focusing on timing analysis and library generation for high-speed serial IO interfaces. With 10 years of experience in Design for Test, Static Timing Analysis, and Logic Design, they have worked with technologies ranging from 180nm to 90nm. Prior to Intel, Vijaya held positions at GDA Technologies Inc, Kawasaki Microelectronics, and RealChip, where they developed DFT methodologies, implemented DFT structures, and engaged in logic design and synthesis. Vijaya is pursuing a Master of Science in Electrical Engineering with a focus on VLSI Chip Design at Northwestern Polytechnic University, having previously earned a Bachelor’s degree in Electronics and Communication Engineering from Mahatma Gandhi University.