Wei-Lun Jen is an experienced engineering professional currently serving as an Engineering TD Manager at Intel Corporation since September 2009, focusing on substrate pathfinding integration. Previously, Wei-Lun held the role of Senior Packaging Engineer at Intel, specializing in substrate pathfinding integration and lithographic processes. Wei-Lun's background includes a Graduate Research Assistant position at the University of Texas at Austin, where research centered on nanoimprint procedures and simulation modeling for multi-level structures. Early career experience includes roles as a Process Engineer at Intel, a Technical Intern at 3M, and an NSF Undergraduate Research Intern at IBM. Wei-Lun earned a PhD in Chemical Engineering from the University of Texas at Austin, further enhancing expertise in the field.
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