Xiang Li is a Principal Engineer at Intel Corporation, focusing on memory and I/O technologies and standards. Previously, they served as a Sr. Staff Engineer, leading the development of DDR5 connectors and contributing to industry standards as the chair of the JEDEC JC11.14 committee. Their experience also includes significant work on USB Type-C specifications and various connector developments, resulting in 92 granted patents and nearly 40 published papers. Xiang holds a Ph.D. in Solid Mechanics from the University of Massachusetts Lowell and has received multiple accolades, including the Intel Achievement Award and the JEDEC Technical Recognition Award.
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