Yu-Shiang Lin is a Principal Engineer at Intel Corporation, where they focus on 3DIC design methodology, simulation, and physical sign-off. They have over 10 years of experience in advanced node synthesis, P&R, and SOC integration. Previously, Yu-Shiang served as a Technical Manager at TSMC and held positions as a Research Staff Member and Post-Doctoral Researcher at IBM. They earned a PhD in Electrical Engineering from the University of Michigan, following a Master's and a Bachelor's degree in the same field from National Taiwan University.
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