Zuoguo Wu

Zuoguo Wu is a seasoned engineering professional with extensive experience in the development of high-speed I/O interfaces, currently serving as Co-Chair of the Electrical Work Group at Universal Chiplet Interconnect Express since February 2024. With a tenure at Intel Corporation starting in January 2003, Zuoguo has held positions as Senior Principal Engineer and Manager, leading the development of UCIe, PCIe, and CXL protocols, as well as team supervision. Previous roles at Intel included Principal Engineer, where the focus was on next-generation I/O interface architecture, and Hardware Architect, responsible for high-speed analog circuit development. Zuoguo has also worked at Utmost Technologies and Microtune, where contributions included designing a 10Gb/s CMOS serial communication transceiver and wireless LAN transceiver ICs, respectively. Early career experience includes positions at Texas Instruments and Micropac Industries, emphasizing design and testing of mixed-signal and power management circuits. Zuoguo holds a Ph.D. in Electrical Engineering from Texas A&M University and a B.S. in Physics from the University of Science and Technology of China.