Yogesh Thyagaraj is an FPGA Developer at Jio since August 2022, contributing to the 5G Low PHY Team with a focus on RTL Design, Synthesis, and Bit File generation, specifically on MRU projects utilizing the Xilinx ZCU670 FPGA board. Prior to this role, Yogesh served as a QA Automation Engineer at Parallel Wireless from May 2021 to August 2022 and completed a position as an Embedded Software Trainee at Volvo Group Trucks Technology from August 2019 to August 2020. Yogesh holds a Master of Technology (MTech) in VLSI Design and Embedded Systems from Dayananda Sagar College of Engineering, obtained in 2020, and a Bachelor of Engineering (BE) in Electronics and Communications Engineering from Atria Institute of Technology, completed in 2018.
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