Vishnu Jayapal

Vishnu Jayapal is a seasoned electrical engineer specializing in FPGA design and development. Currently serving as a Senior FPGA Designer at Keysight Technologies since August 2018, Vishnu focuses on high-speed packet processing, IP development, and System Verilog. Previously, Vishnu worked as an FPGA Design Engineer at Caterpillar Inc., where responsibilities included RTL development and algorithm development utilizing VHDL. Earlier experience includes serving as a Senior Design Engineer and Design Engineer at CoreEL Technologies, with expertise in system design, FPGA development, and board design. Vishnu holds a Master's Degree in Electrical Engineering (VLSI) from the University of Cincinnati and a Bachelor's Degree in Electrical, Electronics and Communications Engineering from Amrita Vishwa Vidyapeetham.