Rish Patel

Rish Patel is an experienced Electrical Design Engineer with over a decade of expertise in the semiconductor and communications industries. Currently employed at KLA-Tencor since January 2012, Rish has implemented FPGA designs for wafer inspection tools, focusing on die-image alignment systems. Previous experience includes a role as a Design Engineer at Cisco Systems, where Rish optimized SerDes interfaces, and a stint at Xilinx characterized Virtex-5 FPGA SEU macros while developing application documentation. Early career activities involved firmware engineering at Performance Technologies and an internship at Xilinx. Rish holds a Master’s degree in Electrical Engineering from Santa Clara University and a Bachelor’s degree in Computer Engineering from California Polytechnic State University-San Luis Obispo.