Sanjay Singh

Sanjay Singh is a Senior Embedded Systems Engineer specializing in FPGA Design and Verification at Lam Research since August 2022, where responsibilities include utilizing SystemVerilog and UVM methodology for verifying FPGA designs and driving verification solution requirements and implementation. Previously, Sanjay served as a Teaching Assistant at Greater Noida Institute of Technology from December 2020 to November 2022, supporting the electronics and communication department and assisting students in hands-on labs. An internship at Maven Silicon involved a 32-bit RISC-V ISA Design Project and mentoring over 150 Advanced VLSI Design and Verification trainees, emphasizing UVM and SystemVerilog skills. Sanjay holds an M.Tech in VLSI Design from the Greater Noida Institute of Technology and a B.Tech in Electronics and Communication from Galgotias College of Engineering and Technology.