Peter Frey

Peter Frey is a Senior Software Engineer at Lattice Semiconductor, where responsibilities include ownership of the software architecture and synthesis flow for FPGA development. Previously, Peter served as a Member of the Technical Staff at Cerebras Systems, leading hardware debug efforts and performance analysis. At Xilinx, Peter worked as a Principal Software Product Application Engineer, enhancing the Vitis Software Product and developing new features for FPGA applications. Peter's career began at Cadence, where contributions spanned from architecting high-level synthesis tools to leading teams in mixed-signal simulation. Peter holds a PhD in Computer Engineering and Computer Science from the University of Cincinnati.