Mark Noble

Mark Noble is a Contract FPGA Consultant who has been involved in FPGA design and development for various high-speed applications. They have held positions at companies such as Leonardo, where they currently design and develop FPGA solutions for new products, and Calnex Solutions, where they modified and developed IP code for network testing products. Mark's extensive experience includes roles at Xilinx, RFEL Ltd, and Toshiba Research Europe, focusing on high-speed interfacing and FPGA design using tools like Vivado. They hold dual Bachelor of Engineering degrees in Electrical and Electronics Engineering from Edinburgh University and the University of Northumbria.