Deepak Garg is a seasoned professional with over 18 years of experience in the semiconductor industry. They hold an MBA in International Business from IIFT Delhi and a BTech from NIT Warangal. Currently serving as the Leader of Physical Design & Signoff at L&T Semiconductor Technologies, Deepak previously held prominent roles at Intel Corporation, Qualcomm, and ST MicroElectronics. Their technical expertise encompasses a range of areas including SoC implementation, static timing analysis, and risk management. Deepak has also contributed to academia as a lecturer in digital design and electronics at various prestigious institutions.
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