Chen Yuan

Chen Yuan is currently a Senior Staff Engineer in Analog IC Design at Marvell Technology. They previously held positions as an Analog/Mixed Signal Engineer at Marvell Semiconductor and an intern at Intel Labs, where they contributed to advancements in clock distribution and high-speed receivers. Chen served as a Research Assistant at the University of British Columbia, focusing on innovative PLL architectures and a low-power full-duplex wireline transceiver, with their work published in IEEE Transactions on Circuits and Systems. They hold a Bachelor's degree in Electrical and Electronics Engineering from Xidian University and a Master's degree in Integrated Circuit Design from the University of British Columbia, where they are also pursuing a PhD.