Deepa Rajendra is a passionate Physical Design Engineer with over 7 years of experience in the VLSI industry. Currently serving as a Staff Engineer at Marvell India Pvt Ltd, they have contributed to eight successful project tape-outs spanning various technology nodes from 28nm to 5nm. Deepa holds a Master's degree in VLSI Design and Embedded Systems from CMR Institute of Technology and a Bachelor's degree in Electronics and Communication from HKBK College of Engineering. Their expertise includes synthesis, block-level PNR, and physical verification, utilizing tools from both Cadence and Synopsys.
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