Dongwei Ge

Dongwei Ge is a Principal Design Engineer at Marvell Technology, where they focus on enterprise SSD controller projects and perform sub-system and block level Static Timing Analysis. Previously, they worked as a SOC Design Engineer at Intel Corporation, contributing to both the Xeon and Xeon Phi processor designs, and was an ASIC Design Engineer at Marvell Semiconductor. Dongwei holds a Master of Science in Electrical and Electronics Engineering from Columbia University and a Bachelor's Degree in Microelectronics Engineering from Xi'an Jiaotong University. Their expertise includes advanced chip level physical design, timing closure, and low power physical design techniques.