Matthew Ernest

Matthew Ernest is a VLSI circuit design engineer with extensive experience in microprocessor design, specializing in semiconductor processes ranging from 65nm to 5nm. They have provided register file designs and design training for Intel Big Core and SOC projects while contributing to semi-automated array layout methodology. Currently, as a Senior Staff Engineer at Marvell Semiconductor, they focus on memory IP development, power analysis, and timing characterization. Matthew earned a PhD in Electrical Engineering from Rensselaer Polytechnic Institute, where they also completed both a Master's and a Bachelor's degree in related fields.